Consider a pipelined processor with the following four stages
IF: Instruction Fetch
ID: Instruction Decode and Operand Fetch
EX: executed
WB: Write Back
The IF, ID and WB stagestake one clock cycle each to complete the operation. The ADD and SUB instructions need 1 clock cycle and the MUL instruction need 3 clock cycles in the EX stage. Operand forwarding is usedin the pipelined processor. What is the number of clock cycles taken to complete the following sequence of instructions?
ADD R2, R1, RO R2 $$\leftarrow$$ R1 + R0
MUL R4, R3, R2 R4 $$\leftarrow$$ R3 * R2
SUB R6, R5, R4 R6 $$\leftarrow$$ R5 - R4